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SN65LVDS20 SN65LVP20
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SLLS620A - JUNE 2004 - REVISED SEPTEMBER 2005
LVPECL AND LVDS REPEATER/TRANSLATOR WITH ENABLE
FEATURES
* * Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs Signaling Rates to 4 Gbps or Clock Rates to 2 GHz - 120-ps Output Transition Times - Less than 45 ps Total Jitter - Less than 630 ps Propagation Delay Times * * 2.5-V or 3.3-V Supply Operation 2-mm x 2-mm Small-Outline No-Lead Package
APPLICATIONS
* * PECL-to-LVDS Translation Data or Clock Signal Amplification
DESCRIPTION
The SN65LVDS20 and SN65LVP20 are a high-speed differential receiver and driver connected as a repeater. The receiver accepts low-voltage positive-emitter-coupled logic (PECL) at signaling rates up to 4 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter. The outputs of the SN65LVDS20 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDP20 are compatible with low-voltage PECL levels. A low-level input to EN enables the outputs. A high-level input puts the output into a high-impedance state. Both outputs are designed to drive differential transmission lines with nominally 100- characteristic impedance. Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended PECL input signals. When not used, VBB should be unconnected or open. All devices are characterized for operation from -40C to 85C. FUNCTION DIAGRAM
EN A B VCC IN GND 9
Scale = 50 ps/div
Y Z
6
OUT
4
VBB
Figure 1. SN65LVDS20 Output Eye Pattern With 4-Gbps PRBS Input
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Scale = 75 mV/div
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Copyright (c) 2004-2005, Texas Instruments Incorporated
SN65LVDS20 SN65LVP20
SLLS620A - JUNE 2004 - REVISED SEPTEMBER 2005
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS (1)
INPUT Differential Differential (1) OUTPUT LVDS LVPECL PART NUMBER SN65LVDS20 SN65LVP20 PART MARKING E8 E7
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VCC VI VO IO Supply voltage Input voltage Output voltage VBB output current HBM electrostatic discharge (3) CDM electrostatic discharge (4) Continuous power dissipation (1) (2) (3) (4)
(2) (1)
UNIT -0.5 V to 4 V -0.5 V to VCC + 0.5 V -0.5 V to VCC + 0.5 V 0.5 mA 3 kV 1500 V See Power Dissipation Ratings Table
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground (see Figure 2). Tested in accordance with JEDEC Standard 22, Test Method A114-A-7 Tested in accordance with JEDEC Standard 22, Test Method C101
DISSIPATION RATINGS
PACKAGE DRF TA < 25C POWER RATING 403 mW OPERATING FACTOR ABOVE TA = 25C 4.0 mW/C TA = 85C POWER RATING 161 mW
RECOMMENDED OPERATING CONDITIONS
MIN VCC VIC |VID| VIH VIL IO RL TA (1) Supply Voltage Common-mode input voltage (VIA + VIB)/2 Differential input voltage magnitude, |VIA - VIB| High-level input voltage, EN Low-level input voltage, EN Output current to VBB Differential load resistance Operating free-air temperature 2.375 1.2 0.08 2 0 -400 (1) 90 -40 NOM 2.5 or 3.3 MAX 3.6 VCC - (VID/2) 1 VCC 0.8 400 132 85 UNIT V V V V V A C
The algebraic convention, where the least positive (more negative) value is designated minimum, is used in this data sheet.
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SN65LVDS20 SN65LVP20
SLLS620A - JUNE 2004 - REVISED SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS RL = 100 , EN at 0 V, Other inputs open ICC Supply current Outputs unloaded, EN at 0 V, Other inputs open RL = 100 , EN at 0 V, 2-GHz 50%-duty-cycle square-wave input 50 from Y and Z to VCC - 2 V, EN at 0 V, 2-GHz 50%-duty-cycle square-wave input IBB = 400 A VI = 2 V VI = VCC VI = 0.8 V VI = GND VCC - 1.44 -20 -20 -20 -20 MIN TYP (1) 35 19 116 MAX 45 mA 24 160 mW 63 VCC - 1.35 86 VCC - 1.25 20 20 20 20 A V UNIT
Device power dissipation, SN65LVDS20 PD Device power dissipation, SN65LVP20 Reference voltage High-level input current, EN High-level input current, A or B Low-level input current, EN Low-level input current, A or B Differential output voltage magnitude, |VOY - VOZ| Change in differential output voltage magnitude between logic states Steady-state common-mode output voltage (see Figure 3) Change in steady-state common-mode output voltage between logic states Peak-to-peak common-mode output voltage High-impedance output current Short-circuit output current Differential short-circuit output current, |IOY - IOZ|
VBB IIH IIAH or IIBH IIL IIAL or IIBL
SN65LVDS20 OUTPUT CHARACTERISTICS (see Figure 2) |VOD| |VOD| VOC(SS) VOC(SS) VOC(PP) IOYZ or IOZZ IOYS or IOZS IOS(D) 247 See Figure 2 1.125 -50 See Figure 3 50 EN at VCC, VO = 0 V or VCC EN at 0 V, VOY or VOZ = 0 V EN at 0 V, VOY = VOZ -1 -62 -12 100 1 62 12 mA A 340 454 mV 50 1.375 50 mV V
SN65LVP20 OUTPUT CHARACTERISTICS (see Figure 2) VOYH or VOZH VOYL or VOZL VOYL or VOZL |VOD| IOYZ or IOZZ (1) High-level output voltage Low-level output voltage Low-level output voltage Differential output voltage magnitude, |VOH - VOL| High-impedance output current EN at VCC, VO = 0 V or VCC 3.3 V; 50 from Y and Z to VCC - 2 V 2.5 V; 50 from Y and Z to VCC - 2 V VCC - 1.05 VCC - 1.83 VCC - 1.88 0.6 -1 0.8 VCC - 0.82 VCC - 1.57 V VCC - 1.57 1 1 A
Typical values are at room temperature and with a VCC of 3.3 V.
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SN65LVDS20 SN65LVP20
SLLS620A - JUNE 2004 - REVISED SEPTEMBER 2005
www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER tPLH tPHL tSK(P) tSK(PP) tr tf tjit(per) tjit(cc) tjit(p-p) tjit(ph) tPHZ tPLZ tPZH tPZL Differential propagation delay time, low-to-high-level output Differential propagation delay time, high-level-to-low-level output Pulse skew, |tPLH - tPHL| Part-to-part skew
(2)
TEST CONDITIONS
MIN TYP (1) 300 450 450
MAX 630 630 20
UNIT
See Figure 2 and Figure 4
300
ps
VCC = 3.3 V VCC = 2.5 V LVDS, See Figure 2 and Figure 4 LVPECL, See Figure 2 and Figure 4 LVDS, See Figure 2 and Figure 4 LVPECL, See Figure 2 and Figure 4 2-GHz 50%-duty-cycle square-wave input, See Figure 5 LVDS; 4 Gbps PRBS, 223- 1 run length, See Figure 5 155.52 MHz 622.08 MHz 85 92 85 92 2 13 37 0.62 0.14
80 130 115 120 115 120 3 16 45
ps ps ps ps ps ps
20%-to-80% differential signal rise time 20%-to-80% differential signal fall time RMS period jitter (3) Peak cycle-to-cycle jitter Peak-to-peak jitter Intrinsic phase jitter Propagation delay time, high-level-to-high-impedance output Propagation delay time, low-level-to-high-impedance output Propagation delay time, high-impedance-to-high-level output Propagation delay time, high-impedance-to-low-level output
(4)
30 30 See Figure 2 and Figure 6 30 30 ns
(1) (2) (3) (4)
Typical values are at room temperature and with a VCC of 3.3 V. Part-to-part skew is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles. Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles, over a random sample of 1,000 adjacent cycle pairs.
PARAMETER MEASUREMENT INFORMATION
ICC 1 IIA IIB 2 3 5 II VIA VIB VI NC A B EN VCC IBB I OZ I OY + VOY - + VOZ - + VBB - 50 S1 50 + VOC - CL VCC - 2 V
8 4 VCC V BB 6 Z D.U.T. 7 Y GND 9
(1) (2)
CL is the instrumentation and test fixture capacitance. S1 is open for the SN65LVDS20 and closed for the SN65LVP20.
Figure 2. Output Voltage Test Circuit and Voltage and Current Definitions
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SN65LVDS20 SN65LVP20
SLLS620A - JUNE 2004 - REVISED SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
INPUT dVOC(SS) VOC(PP)
VOC
Figure 3. VOC Definitions
VCC 1.2 V VIA 1.125 V 1.5 V
VIB t PHL VOY - VOZ 80% 50% tf tr 100% t PLH
20%
Figure 4. Propagation Delay and Transition Time Test Waveforms
50 W Cable, X + Y cm, SMA Coax Connectors, 4 Places
HP3104 Pattern Generator Note A
Device Under Test
TDS Oscilloscope with TJIT3 Analysis Pack 50 W 50 W
DC
Figure 5. Jitter Measurement Setup
5
SN65LVDS20 SN65LVP20
SLLS620A - JUNE 2004 - REVISED SEPTEMBER 2005
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC 1.2 V VIA 1.5 V
VIB VI to EN
2V 1.4 V t PZH t PHZ t PZL t PLZ 0V 0.8 V
VOY - VOZ 50%
80%
100%
20%
Figure 6. Enable and Disable Time Test Waveforms
DEVICE INFORMATION
FUNCTION TABLE (1)
A H L H L X Open X (1) B H H L L X Open X EN L L L L H L Open Y ? L H ? Z ? ? Z ? H L ? Z ? ?
H = high, L = low, Z = high impedance, ? = indeterminate
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SN65LVDS20 SN65LVP20
SLLS620A - JUNE 2004 - REVISED SEPTEMBER 2005
TOP VIEW
1
4
9
8
5 BOTTOM VIEW
Package Pin Assignments - Numerical Listing
PIN 1 2 3 4 5 SIGNAL NC A B VBB EN PIN 6 7 8 9 SIGNAL Z Y VCC GND
Package Pin Assignments - Alphabetical Listing
SIGNAL A B EN GND NC PIN 2 3 5 9 1 SIGNAL VBB VCC Y Z PIN 4 8 7 6
7
SN65LVDS20 SN65LVP20
SLLS620A - JUNE 2004 - REVISED SEPTEMBER 2005
www.ti.com
TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs FREQUENCY
60 60
SUPPLY CURRENT vs FREE-AIR TEMPERATURE
I CC - Supply Current - mA
LVP20 = Loaded
I CC - Supply Current - mA
50
50
LVP20 = Loaded
40
LVDS20
40
LVDS20
30
30
20
20
10 0 400 800 1200 1600 2000 f - Frequency - MHz
10 -40 -20 0 20 40 60 80 100 TA - Free-Air Temperature - C
Figure 7. DIFFERENTIAL OUTPUT VOLTAGE vs FREQUENCY
V OD - Differential Output Voltage - mV 900 800 tr/tf - Rise/Fall Time - ps 700 600 500 400 300 200 100 0 0 500 1000 1500 2000 2500 3000 3500 4000 f - Frequency - MHz 65 -40 LVDS20 LVP20 97 105
Figure 8. LVDS20 RISE/FALL TIME vs FREE-AIR TEMPERATURE
89
tr tf
81
73
-20 0 20 40 60 80 TA - Free-Air Temperature - C
100
Figure 9. LVP20 RISE/FALL TIME vs FREE-AIR TEMPERATURE
105
Figure 10. LVDS20 PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE
500
tr/tf - Rise/Fall Time - ps
97 tf 89 tr
Propagation Delay Time - ps
476 tPHL 452 tPLH 428
81
73
404
65 -40
-20
0
20
40
60
80
100
380
-40
-20
0
20
40
60
80
100
TA - Free-Air Temperature - C
TA - Free-Air Temperature - C
Figure 11.
Figure 12.
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SN65LVDS20 SN65LVP20
SLLS620A - JUNE 2004 - REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
LVP20 PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE
500 5
PERIOD JITTER vs FREQUENCY
Propagation Delay Time - ps
476
tPHL Period Jitter - ps
4
452 tPLH 428
3 LVDS20 2 LVP20 1
404
380 -40
0 -20 0 20 40 60 80 100 0 400 800 1200 1600 2000 TA - Free-Air Temperature - C f - Frequency - MHz
Figure 13. PEAK-TO-PEAK JITTER vs FREQUENCY
25 50
Figure 14. PEAK-TO-PEAK JITTER vs DATA RATE
Peak-to-Peak Jitter - ps
20 LVDS20 15 LVP20 10 Peak-to-Peak Jitter - ps
40 LVP20 30
20 LVDS20 10
5
0 0 400 800 1200 1600 f - Frequency - MHz 2000
0 0 800 1600 2400 3200 4000 Data Rate - Mbps
Figure 15.
Figure 16.
Scale = 75 mV/div
Scale = 50 ps/div
Scale = 175 mV/div
Scale = 50 ps/div
Figure 17. LVDS20 4-Gbps, 223 - 1 PRBS
Figure 18. LVP20 4-Gbps, 223 - 1 PRBS
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SN65LVDS20 SN65LVP20
SLLS620A - JUNE 2004 - REVISED SEPTEMBER 2005
www.ti.com
TYPICAL CHARACTERISTICS (continued)
PHASE NOISE OF SN65LVP20
-40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 100 1k 10 k 100 k 1M 10 M 100 M Blue = Device Green = Source -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 100 1k 10 k 100 k 1M 10 M 100 M Blue = Device Green = Source
PHASE NOISE OF SN65LVP20
Figure 19. Frequency Offset From 155.52 MHz Carrier
Figure 20. Frequency Offset From 622.08 MHz Carrier
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SN65LVDS20 SN65LVP20
SLLS620A - JUNE 2004 - REVISED SEPTEMBER 2005
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
OUTPUT LVP20 VCC VCC VCC OUTPUT LVDS20 VCC VCC
R
R
Y VCC 7V Y Z
Z 7V 7V
7V
ENABLE
VCC
400
300 k 7V
INPUT VCC OUTPUT VBB VCC VCC VCC
A
B
VBB
VBB
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2005
PACKAGING INFORMATION
Orderable Device SN65LVDS20DRFR SN65LVDS20DRFRG4 SN65LVDS20DRFT SN65LVDS20DRFTG4 SN65LVP20DRFR SN65LVP20DRFRG4 SN65LVP20DRFT
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type SON SON SON SON SON SON SON
Package Drawing DRF DRF DRF DRF DRF DRF DRF
Pins Package Eco Plan (2) Qty 8 8 8 8 8 8 8 3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Lead/Ball Finish CU NIPD CU NIPD CU NIPD CU NIPD CU NIPD CU NIPD CU NIPD
MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 250 Green (RoHS & no Sb/Br)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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